The present invention relates to a level shift circuit and a driver circuit having the level shift circuit.
In recent years, displays using various display devices such as displays using liquid crystal display devices or organic EL elements have been developed in a field of the display devices. A higher quality (multi-grayscale) has been demanded for those display devices, and there is a tendency that a voltage amplitude of a scanning signal or a grayscale signal becomes increased. For that reason, higher voltage has been required for the respective output parts of a row driver that drives scanning lines of a display panel, and a column driver that drives data lines of the display panel according to the grayscale signal.
On the other hand, various control signals and a video data signal, which are supplied from a display controller to the row driver (scanning driver) and the column driver (data driver), need high-speed transfer and low EMI (electromagnetic interference) with the use of a small number of wirings. Those signals are being lowered in voltage amplitude. Similarly, in the interiors of the row driver and the column driver, in order to suppress an increase in the area (increase in the costs) of a logic circuit that processes data of the amount increased attributable to higher definition and higher number of multi-grayscale, a fine process is applied with the result that a tendency that a supply voltage of the logic circuit is decreased. That is, the row driver and the column driver need a low voltage in an input part and a high voltage in an output part.
For that reason, in the level shift circuit that converts a low voltage signal of the input part into a high voltage signal of the output part, a low amplitude signal must be converted into a high amplitude signal at a high speed.
FIG. 11 is a diagram illustrating an example of a typical configuration of a level shift circuit that converts the low amplitude signal into the high amplitude signal (refer to Japanese Unexamined Patent Publication No. 2009-188734. The level shift circuit includes p-channel MOS transistors P1 and P2 that function as charge elements of output terminals W1 and W2, n-channel MOS transistors N1 and N2 that function as discharge elements of the output terminals W1 and W2, and an inverter INV0.
The p-channel MOS transistors P1 and P2 have respective sources coupled to a high potential side supply terminal VDD3, respective gates coupled to the output terminals W2 and W1, and respective drains coupled to the output terminals W1 and W2. The p-channel MOS transistors P1 and P2 have respective gates receiving output signals OUT and OUTB of a high amplitude (VSS-VDD3) output from the output terminals W2 and W1.
The n-channel MOS transistors N1 and N2 have respective sources coupled to a low potential side supply terminal VSS, respective drains coupled to the output terminals W1 and W2, and respective gates receiving an input signal IN of a low amplitude (for example, a binary signal of a voltage sufficiently lower than VSS and VDD3), and an inversion signal thereof (both are low amplitude signals).
With the above circuit configuration, the level shift circuit outputs an inversed-phase signal OUTB of the output signal OUT having the high amplitude upon receiving the signal IN of the lower amplitude.